In a conventional metal oxide semiconductor field effect transistor (MOSFET), the source, channel, and drain structures are constructed adjacent to each other within the same plane. The gate dielectric is formed on the channel area and the gate electrode is deposited on the gate dielectric. The transistor is controlled by applying a voltage to the gate electrode thereby allowing a current to flow through the channel between source and drain. The area necessary to support these structures in a plane constrains the number of transistors that can be placed within the limited area of a semiconductor chip. Semiconductor manufacturers increase the packing density of transistors by scaling down the size of the transistor at each generation of technology.
With advances in technology, the physical dimensions of the gate dielectric thickness, the gate length, and the gate oxide thickness have been reduced significantly. Contemporary manufacturing methods currently allow semiconductors to be produced with a transistor gate length of 45 nanometers (nm) and a gate oxide thickness of about 1.2 nm. One conventional gate oxide, silicon dioxide, exhibits reliability issues when only a few atomic layers thick. Additionally, this very thin gate oxide allows leakage current to pass when the device is in an off state, thereby leading to high levels of power consumption and excess heat generation in the semiconductor chip.
Alternative gate dielectric materials have been introduced to help alleviate this problem. However, due to material incompatibility problems, the alternative gate dielectric materials have necessitated a change in gate electrode materials. The polysilicon that has been used as a gate electrode material for many generations is now being replaced with a metal gate. Fabrication of the device using a metal gate instead of a polysilicon gate allows the threshold voltage of a transistor to be better controlled.
An alternative to the standard methods of building planar MOSFETs has been proposed to help alleviate some of the physical barriers to scaling down existing designs. These proposals involve the construction of three dimensional MOSFETs either in the form of a dual-gate transistor (FinFET) or as a tri-gate transistor as a replacement for the conventional planar MOSFET.
Three-dimensional transistor designs such as the dual-gate FinFET and the tri-gate transistor allow tighter packing of the same number of transistors on a semiconductor chip by using vertical or angled surfaces for the gates. The designers use vertical space to accommodate the extra transistor gates, which is analogous to building multi-level buildings as opposed to building single story buildings over a larger plot of land. In a dual-gate FinFET, two gates are oriented along a very narrow strip of silicon known as a fin. The two gates have equivalent lengths because they are located along opposite sides of the fin. The physical size of the fin is typically on the order of 10 nm in width and 50 nm in height. A tri-gate device consists of three gates on a semiconductor body whereby the physical dimensions of the sides of the semiconductor body are equal, resulting in three equivalent transistor gate widths on the same semiconductor body.
Since the tri-gate device has one top gate and two side gates, the overall threshold voltage (Vt) of the tri-gate device is a function of the Vt contributed by the top gate and the Vt for each of the two side gates. The Vt of a transistor is a critical parameter in the operation of the transistor. When a voltage is applied to a gate, the electrons in the substrate become concentrated in the region of the substrate nearest the gate creating a depletion region, or a region where the concentration of electrons are equal to the electron holes. If the voltage applied to the gate is below the threshold voltage, the transistor will remain in an off state. If the voltage applied to the gate is above the threshold voltage, then the transistor is turned on and current is allowed to flow from the source to the drain.
The Vt is a function of the materials used for the conductor, such as a polysilicon layer and a metal layer, along with the respective thicknesses of these layers. One problem with the current method of fabricating a tri-gate device is that the Vt for the top gate may be different than the Vt contributed by each of the two side gates. As a result, when a tri-gate device with equal width gates on the top and two sides of the device is scaled, the Vt for the top gate scales differently than the Vt contributed by the two side gates. It would be an advance in the art to construct a tri-gate device whose physical dimensions can be scaled while maintaining an equivalent Vt on all three gates.